Methods for etching a dielectric barrier layer in a dual damascene structure
US9299577B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2014 |
| Grant date | Mar 29, 2016 |
| Priority date | — |
| Expiry date | Feb 22, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76813
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for eliminating early exposure of a conductive layer in a dual damascene structure and for etching a dielectric barrier layer in the dual damascene structure are provided. In one embodiment, a method for etching a dielectric barrier layer disposed on a substrate includes patterning a substrate having a dielectric bulk insulating layer disposed on a dielectric barrier layer using a hardmask layer disposed on the dielectric bulk insulating layer as an etching mask, exposing a portion of the dielectric barrier layer after removing the dielectric bulk insulating layer uncovered by the dielectric bulk insulating layer, removing the hardmask layer from the substrate, and subsequently etching the dielectric barrier layer exposed by the dielectric bulk insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.