Integrated circuits with nanowires and methods of manufacturing the same
US9306019B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2014 |
| Grant date | Apr 5, 2016 |
| Priority date | — |
| Expiry date | Aug 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
Abstract
Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming a layered fin overlying a substrate, where the layered fin includes an SiGe layer and an Si layer. The SiGe layer and the Si layer alternate along a height of the layered fin. A dummy gate is formed overlying the substrate and the layered fin, and a source and a drain area formed in contact with the layered fin. The dummy gate is removed to expose the SiGe layer and the Si layer, and the Si layer is removed to produce an SiGe nanowire. A high K dielectric layer that encases the SiGe nanowire between the source and the drain is formed, and a replacement metal gate is formed so that the replacement metal gate encases the high K dielectric layer and the SiGe nanowire between the source and drain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.