On-going reliability monitoring of integrated circuit chips in the field
US9310426B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2012 |
| Grant date | Apr 12, 2016 |
| Priority date | — |
| Expiry date | Mar 17, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is an integrated circuit (IC) chip with a built-in self-test (BIST) architecture that allows for in the field accelerated stress testing. The IC chip can comprise an embedded processor, which selectively alternates operation of an on-chip test block between a stress mode and a test mode whenever the IC chip is powered-on such that, during the stress mode, the test block operates at a higher voltage level than an on-chip functional block and such that, during the test mode, the test block operates at a same voltage level as the functional block and is subjected to testing. Also disclosed are a system, method and computer program product which access the results of such testing from IC chips in a variety of different types of products in order model IC chip performance degradation and to generate IC chip end of life predictions specific to the different types of products.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.