Method of stressing a semiconductor layer
US9318372B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 28, 2014 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Oct 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.