Wirebond recess for stacked die
US9318451B2 · kind B2 · utility
2Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2013 |
| Grant date | Apr 19, 2016 |
| Priority date | — |
| Expiry date | Dec 29, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A first semiconductor device die is provided having a bottom edge incorporating a notch structure that allows sufficient height and width clearance for a wire bond connected to a bond pad on an active surface of a second semiconductor device die upon which the first semiconductor device die is stacked. Use of such notch structures reduces a height of a stack incorporating the first and second semiconductor device die, thereby also reducing a thickness of a semiconductor device package incorporating the stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.