Method and apparatus for massively parallel multi-wafer test
US9335347B2 · kind B2 · utility
2Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2012 |
| Grant date | May 10, 2016 |
| Priority date | — |
| Expiry date | Jun 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R35/005
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed herein is a cost effective, efficient, massively parallel multi-wafer test cell. Additionally, this test cell can be used for both single-touchdown and multiple-touchdown applications. The invention uses a novel “split-cartridge” design, combined with a method for aligning wafers when they are separated from the probe card assembly, to create a cost effective, efficient multi-wafer test cell. A “probe-card stops” design may be used within the cartridge to simplify the overall cartridge design and operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.