Transistor with reduced parasitic capacitance and access resistance of the source and drain, and method of fabrication of the same

US9337350B2 · kind B2 · utility

Assignee

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Nicolas Posseme · Grenoble, FR
• Laurent Grenouillet · Voiron, FR
• Yannick Le Tiec · Crolles, FR
• Maud Vinet · Voiron, FR

Key dates

• Filing date: Dec 26, 2012
• Grant date: May 10, 2016
• Expiry date: Dec 26, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/021

Abstract

A transistor includes an active layer forming a channel for the transistor, an insulating layer disposed facing a lower face of the active layer, a gate turned toward an upper face of the active layer and a source and a drain disposed on both sides of the gate. At least one among the source and the drain extends at least partly through the active layer and into the insulating layer.