Patent · US Active

Method for manufacturing a transistor in which the strain applied to the channel is increased

US9343375B2 · kind B2 · utility

2Cited by

0References

19Claims

0Family size

Assignee

COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

Perrine Batude · Dijon, FR
Frédéric Mazen · Grenoble, FR
Shay Reboh · Grenoble, FR
Benoit Sklenard · Grenoble, FR

Key dates

Filing date	Jul 17, 2015
Grant date	May 17, 2016
Priority date	—
Expiry date	Jul 17, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/797

Abstract

Method of manufacturing a transistor on a layer made of a first crystalline semiconducting material to make a channel, deposited on a dielectric layer, the method including the following steps:

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.