Memory first process flow and device

US9368606B2 · kind B2 · utility

Assignee

• Cypress Semiconductor Corporation · US

Inventors

• Shenqing Fang · Fremont, US
• Chun Chen · San Jose, US
• Unsoon Kim · San Jose, US
• Mark T. Ramsbey · Sunnyvale, US
• Kuo-Tung Chang · Saratoga, US
• Sameer Haddad · San Jose, US
• James Pak · Sunnyvale, US

Key dates

• Filing date: Dec 14, 2012
• Grant date: Jun 14, 2016
• Expiry date: Feb 12, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037

Abstract

Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, a semiconductor device includes a memory gate disposed in a first region of the semiconductor device. The memory gate may include a first gate conductor layer disposed over a charge trapping dielectric. A select gate may be disposed in the first region of the semiconductor device adjacent to a sidewall of the memory gate. A sidewall dielectric may be disposed between the sidewall of the memory gate and the select gate. Additionally, the device may include a logic gate disposed in a second region of the semiconductor device that comprises the first gate conductor layer.