Self aligned via in integrated circuit

US9385078B1 · kind B1 · utility

Assignees

• International Business Machines Corporation · US
• STMICROELECTRONICS, INC. · US
• TOKYO ELECTRON LIMITED · JP

Inventors

• Yannick Feurprier · Watervliet, US
• Joe Lee · Albany, US
• Lars Liebmann · Poughquag, US
• Yann Mignot · Slingerlands, US
• Terry A. Spooner · Clifton Park, US
• Douglas M. Trickett · Altamont, US
• Mehmet Yilmaz · Cupertino, US

Key dates

• Filing date: Mar 9, 2016
• Grant date: Jul 5, 2016
• Expiry date: Mar 9, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.