CMOS structures and processes based on selective thinning

US9391076B1 · kind B1 · utility

Assignee

• Mie Fujitsu Semiconductor Limited · JP

Inventors

• Scott E. Thompson · Gainesville, US
• Thomas Hoffmann · Santa Cruz, US
• Lance Scudder · Sunnyvale, US
• Urupattur C. Sridharan · San Jose, US
• Dalong Zhao · San Jose, US
• Pushkar Ranade · Los Gatos, US
• Michael Duane · Austin, US
• Paul E. Gregory · Palo Alto, US

Key dates

• Filing date: Dec 18, 2014
• Grant date: Jul 12, 2016
• Expiry date: Dec 18, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/856
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods for fabricating semiconductor devices and devices therefrom are provided. A method includes providing a substrate having a semiconducting surface with first and second layers, where the semiconducting surface has a plurality of active regions comprising first and second active regions. In the first active region, the first layer is an undoped layer and the second layer is a highly doped screening layer. The method also includes removing a part of the first layer to reduce a thickness of the substantially undoped layer for at least a portion of the first active region without a corresponding thickness reduction of the first layer in the second active region. The method additionally includes forming semiconductor devices in the plurality of active regions. In the method, the part of the first layer removed is selected based on a threshold voltage adjustment required for the substrate in the portion of the first active region.