FinFETs having strained channels, and methods of fabricating finFETs having strained channels
US9391200B2 · kind B2 · utility
24Cited by
5References
21Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jun 18, 2014 |
| Grant date | Jul 12, 2016 |
| Priority date | — |
| Expiry date | Jul 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/605
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques and structures for controlling etch-back of a finFET fin are described. One or more layers may be deposited over the fin and etched. Etch-back of a planarization layer may be used to determine a self-limited etch height of one or more layers adjacent the fin and a self-limited etch height of the fin. Strain-inducing material may be formed at regions of the etched fin to induce strain in the channel of a finFET.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.