Memory cells with vertically integrated tunnel access device and programmable impedance element

US9391270B1 · kind B1 · utility

Assignee

• Adesto Technologies Corporation · US

Inventors

• Venkatesh P. Gopinath · Planada, US
• Jeffrey A. Shields · Sunnyvale, US
• Yi Ma · Orlando, US
• Chakravarthy Gopalan · Santa Clara, US
• Ming Sung Kwon · Sunnyvale, US
• John Dinh · Dublin, US

Key dates

• Filing date: Oct 31, 2014
• Grant date: Jul 12, 2016
• Expiry date: Oct 31, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B63/30

Abstract

A memory device can include a plurality of memory cells formed over a substrate, each memory cell including a tunnel access device that enables current flow in at least one direction predominantly due to tunneling, and a storage element programmable between different impedance states by a reduction-oxidation reaction within at least one memory layer formed between two electrodes; wherein the tunneling access device and programmable impedance element are vertically stacked over one another.