Method for creating self-aligned compact contacts in an IC device meeting fabrication spacing constraints
US9406775B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2015 |
| Grant date | Aug 2, 2016 |
| Priority date | — |
| Expiry date | Apr 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming a self-aligned gate-cut in close proximity to a gate contact and the resulting device are disclosed. Embodiments include providing a substrate with silicon fins and a metal gate with a nitride-cap perpendicular to and over the fins, with source/drain regions, each with an oxide-cap, on the fins on opposite sides of the gate; forming parallel dielectric lines, separated from each other, perpendicular to and over the gate; forming a photoresist over the parallel dielectric lines, forming an opening in the photoresist exposing a nitride-cap between two fins; removing the exposed nitride-cap exposing an underlying metal gate; removing the exposed metal gate and a remainder of the photoresist; forming low-k dielectric lines between the parallel dielectric lines; removing sections of the parallel dielectric lines; forming perpendicular interconnects between the low-k dielectric lines; removing a remainder of the parallel dielectric lines forming trenches; and filling the trenches with metal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.