Method of forming SGT MOSFETs with improved termination breakdown voltage
US9431495B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Aug 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/117
Abstract
A method of manufacturing a trench power MOSFET device with improved UIS performance and a high avalanche breakdown voltage is disclosed. The method includes performing a first etching of the epitaxial layer to form an active trench with an initial depth in an active area of the semiconductor substrate and a termination trench with a desired depth in a termination area of the semiconductor substrate, wherein the initial depth of the active trench is smaller than the desired depth of the termination trench and performing a second etching to increase the depth of the active trench to a desired depth wherein a depth difference between the desired depth of the active trench and the desired depth of the termination trench is smaller than a depth difference between the initial depth of the active trench and the desired depth of the termination trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.