Integrating transistors with different poly-silicon heights on the same die
US9431503B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Jan 7, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/48
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprises a first poly-silicon region including a first poly-silicon layer, a second poly-silicon layer disposed over the first poly-silicon layer, a first poly-silicon finger associated with the first poly-silicon layer, and a second poly-silicon finger associated with the second poly-silicon layer. The first poly-silicon finger and the second poly-silicon finger are oriented in a substantially orthogonal manner relative to each other. The integrated circuit comprises a second poly-silicon gate region including the first poly-silicon layer. The first polysilicon gate region and the second polysilicon gate region each have different poly-silicon gate structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.