Lithographic stack excluding SiARC and method of using same
US9431528B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | May 19, 2014 |
| Grant date | Aug 30, 2016 |
| Priority date | — |
| Expiry date | Oct 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31138
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lithographic stack over a raised structure (e.g., fin) of a non-planar semiconductor structure, such as a FinFET, includes a bottom layer of spin-on amorphous carbon or spin-on organic planarizing material, a hard mask layer of a nitride and/or an oxide on the spin-on layer, a layer of a developable bottom anti-reflective coating (dBARC) on the hard mask layer, and a top layer of photoresist. The stack is etched to expose and recess the raised structure, and epitaxial structure(s) are grown on the recess.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.