Method for fabricating microelectronic devices with isolation trenches partially formed under active regions
US9437474B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2012 |
| Grant date | Sep 6, 2016 |
| Priority date | — |
| Expiry date | Sep 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.