Method of making a vertical NAND device using a sacrificial layer with air gap and sequential etching of multilayer stacks
US9449982B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2015 |
| Grant date | Sep 20, 2016 |
| Priority date | — |
| Expiry date | Jun 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and forming a sacrificial material portion including an encapsulated cavity. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material portion to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.