Patent · US Active

SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto

US9450073B2 · kind B2 · utility

2Cited by

6References

23Claims

0Family size

Assignee

Advanced Micro Devices, Inc. · US

Inventors

Andy Wei · Queensbury, US
Thorsten Kammler · Radeberg, DE
Roman Boschke · Dresden, DE
Casey Scott · Dresden, DE

Key dates

Filing date	Nov 8, 2007
Grant date	Sep 20, 2016
Priority date	—
Expiry date	May 18, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH10D30/0212
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.