Methods of increasing silicide to epi contact areas and the resulting devices
US9461171B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2014 |
| Grant date | Oct 4, 2016 |
| Priority date | — |
| Expiry date | Jun 4, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, performing an epitaxial deposition process to form an epi semiconductor material on the active region in the source/drain region of the device, performing an etching process on the epi semiconductor material to remove a portion of the epi semiconductor material so as to define at least one epi recess in the epi semiconductor material, forming a metal silicide layer on the upper surface of the epi semiconductor material and in the at least one epi recess in the epi semiconductor material, and forming a conductive structure that is conductively coupled to the metal silicide layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.