Sputter etch processing for heavy metal patterning in integrated circuits
US9484220B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Apr 13, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating one or more conductive lines in an integrated circuit includes providing a layer of copper containing conductive metal in a multi-layer structure fabricated upon a wafer, providing a first hard mask layer over the layer of copper containing conductive metal, performing a first sputter etch of first hard mask layer using a chlorine-based plasma or a sulfur fluoride-based plasma, and performing a second sputter etch of first hard mask layer using a second plasma, wherein a portion of the layer of copper containing conductive metal residing below a portion of the first hard mask layer that remains after the second sputter etch forms the one or more conductive lines. In one embodiment, the second plasma is a fluorocarbon-based plasma.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.