Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer and forming second conductive material on dielectric layer
US9502350B1 · kind B1 · utility
22Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2016 |
| Grant date | Nov 22, 2016 |
| Priority date | — |
| Expiry date | Jan 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53266
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive material to form a patterned first conductive layer, and depositing a dielectric layer on interconnect structure. Aspects also include depositing a second conductive material on the dielectric layer and removing the second conductive material through the top of the second metal liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.