Inventor · Hopewell Junction, NY, US

Samuel S. Choi

53Patents
9h-index
46Co-inventors
74Inventor score

Filing activity: Nov 15, 2004 → Sep 30, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US9502350B1 Interconnect scaling method including forming dielectric layer over subtractively etched first conductive layer and forming second conductive material on dielectric layer Electricity 22 Active
US9601426B1 Interconnect structure having subtractive etch feature and damascene feature Electricity 21 Active
US10177031B2 Subtractive etch interconnects Electricity 19 Active
US7790601B1 Forming interconnects with air gaps Electricity 18 Active
US9171801B2 E-fuse with hybrid metallization Electricity 17 Active
US9536830B2 High performance refractory metal / copper interconnects to eliminate electromigration Electricity 13 Active
US9685404B2 Back-end electrically programmable fuse Electricity 11 Active
US9059170B2 Electronic fuse having a damaged region Electricity 11 Active
US8835305B2 Method of fabricating a profile control in interconnect structures Electricity 10 Active
US9324634B2 Semiconductor interconnect structure having a graphene-based barrier metal layer Electricity 8 Active
US8736020B2 Electronic anti-fuse Electricity 7 Active
US9142506B2 E-fuse structures and methods of manufacture Electricity 7 Active
US9293412B2 Graphene and metal interconnects with reduced contact resistance Electricity 6 Active
US7045464B1 Via reactive ion etching process Electricity 6 Expired
US8962467B2 Metal fuse structure for improved programming capability Emerging Cross-Sectional Technologies 6 Active
US9202743B2 Graphene and metal interconnects Electricity 6 Active
US9852980B2 Interconnect structure having substractive etch feature and damascene feature Electricity 5 Active
US8916461B2 Electronic fuse vias in interconnect structures Electricity 5 Active
US9324635B2 Semiconductor interconnect structure having a graphene-based barrier metal layer Electricity 5 Active
US9536842B2 Structure with air gap crack stop Electricity 4 Active
US8796150B2 Bilayer trench first hardmask structure and process for reduced defectivity Electricity 4 Active
US8138093B2 Method for forming trenches having different widths and the same depth Electricity 4 Active
US9455186B2 Selective local metal cap layer formation for improved electromigration behavior Electricity 4 Active
US9431292B1 Alternate dual damascene method for forming interconnects Electricity 3 Active
US9755016B2 Integration process to form microelectronic or micromechanical structures Electricity 3 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.