Apparatuses and methods for implementing masked write commands

US9508409B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Mark Kalei Hadrick · Boise, US
• Jeffrey P. Wright · Boise, US
• Victor Wong · Boise, US
• Simon J. Lovett · Meridian, US
• Donald M. Morgan · Meridian, US
• William F. Jones · Pittsford, US
• Sujeet Ayyapureddi · Boise, US
• Dean D. Gans · Nampa, US
• Jongtae Kwak · Boise, US

Key dates

• Filing date: Apr 16, 2014
• Grant date: Nov 29, 2016
• Expiry date: Jul 25, 2034

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2207/229
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Apparatuses and methods for implementing masked write commands are disclosed herein. An example apparatus may include a memory bank, a local buffer circuit, and an address control circuit. The local buffer circuit may be associated with the memory bank. The address control circuit may be coupled to the memory bank and configured to receive a command and an address associated with the command. The address control circuit may include a global buffer circuit configured to store the address. The address control circuit may further be configured to delay the command using one of a plurality of command paths based, at least in part, on a write latency and to provide the address stored in the global buffer circuit to the local buffer circuit to be stored therein.