Channel cladding last process flow for forming a channel region on a FinFET device having a reduced size fin in the channel region
US9508853B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 18, 2016 |
| Grant date | Nov 29, 2016 |
| Priority date | — |
| Expiry date | Mar 18, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement epi semiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.