Junction overlap control in a semiconductor device using a sacrificial spacer layer
US9530864B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2014 |
| Grant date | Dec 27, 2016 |
| Priority date | — |
| Expiry date | Jan 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
Abstract
Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.