Source and drain epitaxial semiconductor material integration for high voltage semiconductor devices

US9570555B1 · kind B1 · utility

Assignees

• International Business Machines Corporation · US
• GlobalFoundries Inc. · KY

Inventors

• Balasubramanian Pranatharthiharan · Watervliet, US
• Junli Wang · Slingerlands, US
• Ruilong Xie · Niskayuna, US

Key dates

• Filing date: Oct 29, 2015
• Grant date: Feb 14, 2017
• Expiry date: Oct 29, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215

Abstract

A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having a second pitch, wherein the second pitch is greater than the first pitch. An epitaxial semiconductor material on the first and second set of fin structures. The epitaxial semiconductor material on the first fin structures is merging epitaxial material and the epitaxial material on the second fin structures is non-merging epitaxial material. A dielectric liner is formed atop the epitaxial semiconductor material that is present on the first and second sets of fin structures. The dielectric liner is removed from a portion of the non-merging epitaxial material that is present on the second set of fin structures. A bridging epitaxial semiconductor material is formed on exposed surfaces of the non-merging epitaxial material.