Self-aligned gate tie-down contacts with selective etch stop liner
US9570573B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2015 |
| Grant date | Feb 14, 2017 |
| Priority date | — |
| Expiry date | Aug 10, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a gate tie-down includes exposing an active area to form trench contact openings and forming trench contacts therein. An etch stop layer is formed on the trench contacts and on spacers of adjacent gate structures. An interlevel dielectric (ILD) is deposited to fill over the etch stop layer. The ILD and the etch stop layer on one side of the gate structure are opened up to provide an exposed etch stop layer portion. The gate structure is recessed to expose a gate conductor. The exposed etch stop layer portion is removed. A conductive material is deposited to provide a self-aligned contact down to the trench contact on the one side of the gate structure, to form a gate contact down to the gate conductor and to form a horizontal connection within the ILD over the active area between the gate conductor and the self-aligned contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.