Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation

US9570614B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ravi Pillarisetty · Portland, US
• Sansaptak Dasgupta · Hillsboro, US
• Niti Goel · Portland, US
• Van H. Le · Portland, US
• Marko Radosavljevic · Portland, US
• Gilbert Dewey · Beaverton, US
• Niloy Mukherjee · Beaverton, US
• Matthew V. Metz · Portland, US
• Willy Rachmady · Beaverton, US
• Jack T. Kavalieros · Portland, US
• Benjamin Chu-Kung · Portland, US
• Harold W. Kennel · Portland, US
• Stephen M. Cea · Hillsboro, US
• Robert S. Chau · Beaverton, US

Key dates

• Filing date: Sep 27, 2013
• Grant date: Feb 14, 2017
• Expiry date: Sep 27, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/834
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.