Methods for manufacturing a chip arrangement, methods for manufacturing a chip package, a chip package and chip arrangements

US9576875B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Reinhard Hess · Straubing, DE
• Katharina Umminger · Wenzenbach, DE
• Gabriel Maier · Regensburg, DE
• Markus Menath · Regensburg, DE
• Gunther Mackh · Dresden, DE
• Hannes Eder · Villach, AT
• Alexander Heinrich · Bad Abbach, DE

Key dates

• Filing date: Jan 7, 2015
• Grant date: Feb 21, 2017
• Expiry date: Jan 7, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/00014
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for manufacturing a chip arrangement is provided, the method including: forming a hole in a carrier including at least one chip, wherein forming a hole in the carrier includes: selectively removing carrier material, thereby forming a cavity in the carrier, forming passivation material over one or more cavity walls exposed by the selective removal of the carrier material; selectively removing a portion of the passivation material and further carrier material exposed by the selective removal of the passivation material, wherein a further portion of the passivation material remains over at least one cavity side wall; the method further including subsequently forming a layer over the further portion of passivation material remaining over the at least one cavity side wall.