FinFET and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions
US9577100B2 · kind B2 · utility
13Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2014 |
| Grant date | Feb 21, 2017 |
| Priority date | — |
| Expiry date | Nov 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A semiconductor device including at least one suspended channel structure of a silicon including material, and a gate structure present on the suspended channel structure. At least one gate dielectric layer is present surrounding the suspended channel structure, and at least one gate conductor is present on the at least one gate dielectric layer. Source and drain structures may be composed of a silicon and germanium including material. The source and drain structures are in contact with the source and drain region ends of the suspended channel structure through a silicon cladding layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.