Particle generation suppressor by DC bias modulation
US9593421B2 · kind B2 · utility
55Cited by
8References
10Claims
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Key dates
| Filing date | Oct 15, 2014 |
| Grant date | Mar 14, 2017 |
| Priority date | — |
| Expiry date | Feb 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/334
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Methods for reducing particle generation in a processing chamber are disclosed. The methods generally include generating a plasma between a powered top electrode and a grounded bottom electrode, wherein the top electrode is parallel to the bottom electrode, and applying a constant zero DC bias voltage to the powered top electrode during a film deposition process to minimize the electrical potential difference between the powered top electrode and the plasma and/or the electrical potential difference between the grounded bottom electrode and the plasma.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.