Air gap formation in interconnection structure by implantation process
US9595467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2015 |
| Grant date | Mar 14, 2017 |
| Priority date | — |
| Expiry date | Jan 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5222
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming air gaps in an interconnection structure with desired materials formed on different locations of the interconnection structure using an ion implantation process to define an etching boundary followed by an etching process for semiconductor devices are provided. In one embodiment, a method for forming air gaps in an interconnection structure on a substrate, the method includes implanting ions in a first region of an insulating material disposed on a substrate, leaving a second region without implanted ions, the second region having a first surface interfaced with the first region and a second surface interfaced with the substrate, and performing an etching process to selectively etch the second region away from the substrate, forming an air gap between the first region and the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.