Interconnect structure having subtractive etch feature and damascene feature
US9601426B1 · kind B1 · utility
21Cited by
0References
5Claims
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Assignee
Inventors
Key dates
| Filing date | May 27, 2016 |
| Grant date | Mar 21, 2017 |
| Priority date | — |
| Expiry date | May 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53266
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming an interconnect structure include depositing a first conductive material on a substrate. Aspects include subtractively etching the conductive material to form a patterned first conductive layer, and depositing a dielectric layer on interconnect structure. Aspects also include depositing a second conductive material on the dielectric layer and removing the second conductive material through the top of the second metal liner.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.