Scalable geometry processing within a checkerboard multi-GPU configuration
US9619855B2 · kind B2 · utility
1Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 18, 2011 |
| Grant date | Apr 11, 2017 |
| Priority date | — |
| Expiry date | Jul 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2210/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.