Managing buffered communication between sockets
US9665505B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2014 |
| Grant date | May 30, 2017 |
| Priority date | — |
| Expiry date | Oct 3, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A motherboard includes multiple sockets, each socket configured to accept an integrated circuit. A first integrated circuit in a first socket includes one or more cores and at least one buffer. A second integrated circuit in a second socket includes one or more cores and at least one buffer. Communication circuitry transfers messages to buffers of integrated circuits coupled to different sockets. A first core on the first integrated circuit is configured to send messages corresponding to multiple types of instructions to a second core on the second integrated circuit through the communication circuitry. The buffer of the second integrated circuit is large enough to store a maximum number of instructions of a second type that are allowed to be outstanding from cores on the first integrated circuit at the same time, and still have enough storage space for one or more instructions of a first type.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.