Devices and methods of forming epi for aggressive gate pitch
US9685384B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2016 |
| Grant date | Jun 20, 2017 |
| Priority date | — |
| Expiry date | Jul 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0133
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Devices and methods of fabricating integrated circuit devices for forming epi for aggressive gate pitch are provided. One method includes: obtaining an intermediate semiconductor device having a substrate, a fin structure, a plurality of stacks; etching the spacer between the plurality of stacks; growing, epitaxially, undoped silicon on a top surface of the fin structure between the plurality of stacks; depositing a liner over the undoped silicon and the plurality of stacks; etching to remove the liner and narrow the spacers, wherein the etching forms a wider portion of the spacer at the base of the stacks; etching between the plurality of stacks to remove the undoped silicon and form recesses in the fin structure; and growing, epitaxially, doped silicon between the plurality of stacks and in the fin structure. Also disclosed is an intermediate device formed by the method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.