Three-dimensional semiconductor transistor with gate contact in active region
US9691897B2 · kind B2 · utility
20Cited by
0References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2015 |
| Grant date | Jun 27, 2017 |
| Priority date | — |
| Expiry date | Sep 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional transistor includes a semiconductor substrate, a fin coupled to the substrate, the fin including an active region across a top portion thereof, the active region including a source, a drain and a channel region therebetween. The transistor further includes a gate situated above the channel region, and a gate contact situated in the active region, no portion thereof being electrically coupled to the source or drain. The transistor is achieved by removing a portion of the source/drain contact situated beneath the gate contact during fabrication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.