Patent · US Active

Substrate backside texturing

US9711419B2 · kind B2 · utility

2Cited by

10References

16Claims

0Family size

Assignee

TOKYO ELECTRON LIMITED · JP

Inventors

Carlos A. Fonseca · Lagrangeville, US
Benjamen M. Rathsack · Austin, US
Jeffrey Smith · Clifton Park, US
Anton J. deVilliers · Boise, US
Lior Huli · Albany, US
Teruhiko Kodama · Kochi, JP
Joshua Hooge · Austin, US

Key dates

Filing date	Aug 22, 2015
Grant date	Jul 18, 2017
Priority date	—
Expiry date	Aug 22, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH01L22/20
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Embodiments described relate to a method and apparatus for reducing lithographic distortion. A backside of a semiconductor substrate may be texturized. Then a lithographic process may be performed on the semiconductor substrate having the texturized backside.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.