Methods of forming under device interconnect structures
US9721898B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Oct 4, 2016 |
| Grant date | Aug 1, 2017 |
| Priority date | — |
| Expiry date | Oct 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming microelectronic interconnect under device structures are described. Those methods and structures may include forming a device layer in a first substrate, forming at least one routing layer in a second substrate, and then coupling the first substrate with the second substrate, wherein the first substrate is bonded to the second substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.