Vertical transistor with uniform bottom spacer formed by selective oxidation
US9741626B1 · kind B1 · utility
42Cited by
6References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Oct 20, 2016 |
| Grant date | Aug 22, 2017 |
| Priority date | — |
| Expiry date | Oct 20, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3086
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method of forming a vertical transistor includes forming at least one fin on stacked layers. The stacked layers include a substrate, a doped silicon layer, and an intrinsic layer interposed between the pair of fins and the substrate. The method further includes forming a spacer hardmask over the pair of fins, and forming a bottom spacer. Forming the bottom spacer includes selective oxidation of the SiGe layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.