Stress retention in fins of fin field-effect transistors

US9741856B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Sivananda K. Kanakasabapathy · Niskayuna, US
• Gauri Karve · Cohoes, US
• Juntao Li · Cohoes, US
• Fee Li Lie · Albany, US
• Stuart A. Sieg · Albany, US
• John R. Sporre · Albany, US

Key dates

• Filing date: Dec 2, 2015
• Grant date: Aug 22, 2017
• Expiry date: Dec 2, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a looped spacer on an upper surface of a substrate and adjacent to at least a sidewall of a mandrel. The mandrel may be removed, leaving the looped spacer on the substrate. An exposed portion of the substrate may be removed to form a looped fin below the looped spacer. The spacer may be removed, leaving a looped fin. A looped fin formation may reduce stress relaxation compared to conventional fin formation methods. Embodiments may include forming a gate over a looped portion of a looped fin. Securing a looped portion in position with a gate may decrease stress relaxation in the fin. Thus, a looped fin with a looped portion of the looped fin under a gate may have substantially reduced stress relaxation compared to a conventional fin.