Heterojunction semiconductor device having integrated clamping device
US9748224B2 · kind B2 · utility
5Cited by
4References
31Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 14, 2015 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Sep 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a group III-V transistor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A clamping device is integrated with the group III-V transistor structure and is electrically connected to the first current carrying electrode a third electrode to provide a secondary current path during, for example, an electrical stress event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.