Multi-channel gate-all-around FET
US9748352B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 30, 2015 |
| Grant date | Aug 29, 2017 |
| Priority date | — |
| Expiry date | Dec 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A high performance GAA FET is described in which vertically stacked silicon nanowires carry substantially the same drive current as the fin in a conventional FinFET transistor, but at a lower operating voltage, and with greater reliability. One problem that occurs in existing nanowire GAA FETs is that, when a metal is used to form the wraparound gate, a short circuit can develop between the source and drain regions and the metal gate portion that underlies the channel. The vertically stacked nanowire device described herein, however, avoids such short circuits by forming insulating barriers in contact with the source and drain regions, prior to forming the gate. Through the use of sacrificial films, the fabrication process is almost fully self-aligned, such that only one lithography mask layer is needed, which significantly reduces manufacturing costs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.