Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures
US9761699B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 28, 2015 |
| Grant date | Sep 12, 2017 |
| Priority date | — |
| Expiry date | Feb 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.