Systems and methods for suppressing parasitic plasma and reducing within-wafer non-uniformity
US9793096B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 2015 |
| Grant date | Oct 17, 2017 |
| Priority date | — |
| Expiry date | Mar 11, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J37/32623
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A substrate processing system for depositing film on a substrate includes a processing chamber defining a reaction volume. A showerhead includes a stem portion having one end connected adjacent to an upper surface of the processing chamber. A base portion is connected to an opposite end of the stem portion and extends radially outwardly from the stem portion. The showerhead is configured to introduce at least one of process gas and purge gas into the reaction volume. A plasma generator is configured to selectively generate RF plasma in the reaction volume. An edge tuning system includes a collar and a parasitic plasma reducing element that is located around the stem portion between the collar and an upper surface of the showerhead. The parasitic plasma reducing element is configured to reduce parasitic plasma between the showerhead and the upper surface of the processing chamber.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.