Formation of a bottom source-drain for vertical field-effect transistors

US9799765B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Marc A. Bergendahl · Troy, US
• Kangguo Cheng · Schenectady, US
• Fee Li Lie · Albany, US
• Shogo Mochizuki · Clifton Park, US
• Junli Wang · Slingerlands, US

Key dates

• Filing date: Jun 29, 2016
• Grant date: Oct 24, 2017
• Expiry date: Jun 29, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/151

Abstract

In an embodiment, this invention relates to a vertical field-effect transistor component including a bottom source-drain layer and a method of creating the same. The method of forming a bottom source-drain layer of a vertical field-effect transistor component can comprise forming an anchor structure on a substrate. A sacrificial layer can be deposited on a middle region of the substrate and a channel layer can be deposited on the sacrificial layer. A plurality of vertical fins can be formed on the substrate and the sacrificial layer can be removed such that the plurality of vertical fins in the middle region form a plurality of floating fins having a gap located between the plurality of floating fins and the substrate. The bottom source-drain layer can then be formed such that the bottom source-drain layer fills in the gap.