FinFET spacer formation on gate sidewalls, between the channel and source/drain regions
US9806078B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2016 |
| Grant date | Oct 31, 2017 |
| Priority date | — |
| Expiry date | Nov 2, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/834
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
FinFET spacer formation includes, for example, providing an intermediate semiconductor structure having a substrate having one or more fin having a first and a second plurality of gates disposed thereon, and a first plurality of spacers disposed on sides of the first and second plurality of gates, depositing a first liner on the structure, depositing a fill material at a level along inner portions of the first liner between the gates adjacent to the one or more fin, removing outer portions of the first spacers and the first liner away from the fill material, the remaining portions of the first spacers and the first liner defining a first thickness, and depositing a second liner having a second thickness over the gates and over the remaining portions of the first spacers and the first liner, and the fill material, and wherein the first thickness is greater than the second thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.