BiMOS device with a fully self-aligned emitter-silicon and method for manufacturing the same
US9812369B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2016 |
| Grant date | Nov 7, 2017 |
| Priority date | — |
| Expiry date | Mar 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.